1. Field of the Invention
The present invention relates to a flash memory cell and a method for manufacturing the same.
2. Discussion of the Related Art
A flash memory cell is a device fabricated by adopting the merits and principles of EPROM, which has programmable and erasable characteristics, and of EEPROM which has electrically programmable and erasable characteristics. The flash memory cell includes a thin tunnel oxide film formed on a silicon substrate, a floating gate and a control gate stacked on the oxide film, and source and drain regions formed on an exposed portion of the substrate. A dielectric layer is interposed between the floating gate and the control gate. The flash memory cell allows storage of one bit in a single transistor and performs electrical programming and erasing.
The flash memory cell includes a source connecting layer which connects source regions of respective unit cells to form a source line. The source connecting layer can be fabricated by a metal contact method which connects metal contacts to one another after forming the metal contacts in the respective unit cells. However, this method is not suitable for highly integrated devices due to contact margin. Accordingly, a common source line comprising an impurity diffusion layer formed by a self-aligned source (SAS) process has been increasingly applied so that high integration of devices may be implemented.
Specifically, with a multilayered gate electrode formed on a substrate, the SAS process exposes a source region of each cell by using a separate SAS mask. A field oxide film is then removed by anisotropic etching to form a common source line adjacent cells. The SAS process can reduce the area of each cell in a bit line direction, especially a space between the gate and the source region. Thus, it is a necessary process for a 0.25 μm level technique. The SAS process described above can reduce the area of the cell by about 20%. However, the SAS process has at least one disadvantage. When the SAS process is applied in a memory cell where the common source line is formed along a profile of a trench region, a contact resistance of the source region in each cell is rapidly increased in practice. The resistance of the common source line is increased because as a junction resistance is generated along a feature of the trench region, the length of an actual sheet resistance and a specific resistance of a sidewall in the trench region are increased. Ion implantation is performed such that a relatively small dose of ions is implanted to the sidewall of the trench region. Thus, the resistance of the sidewall is considerably increased.
For most memory cells having a level of 0.25 μm to 0.18 μm or less, a shallow-trench isolation process is used as an isolation technique. The shallow-trench isolation process and the SAS process are necessary processes that reduce the area of the cells in a word line direction and in a bit line direction, respectively. However, when both processes are simultaneously applied, a problem occurs in that a source resistance is remarkably increased.
Since the flash memory cell employs an internal high voltage, the depth of the trench region is increased corresponding to the reduction in the area of the cell. Thus, the length of the common source line gradually increases, thereby providing a disadvantageous effect to the source resistance. For an embedded flash memory cell, detrimental effects occur, such as deterioration in programming characteristics and read speed.